1. Field of the Invention
The present invention relates to a capacitance cell, a semiconductor device, and a capacitance element arranging method when forming a capacitance element by use of multilayer wiring, and, more particularly to a capacitance cell, a semiconductor device, and a capacitance element arranging method that are capable of effectively arranging capacitance elements in non-wired areas on-a semiconductor device.
2. Description of Related Art
A capacitance element such as a decoupling capacitance provided for removing power supply noise has been formed by use of gate oxide films of MOS transistors when being formed inside of a semiconductor element. However, in recent years, owing to miniaturization of processing technologies, influence of a gate leak current can no longer be ignored. When a decoupling capacitance is formed of a capacitance element using a gate oxide film, increase in standby current is unavoidable in actual circumstances.
Therefore, in micro-processing, in place of capacitance elements using gate oxide films, capacitance elements each formed of a pair of wiring layers and an interlayer insulating film with less of a leak current sandwiched between the wiring layers have been proposed in various modes. Japanese unexamined patent publication No. 2003-249559 and Japanese unexamined patent publication No. 2004-241762 are examples of these.
In a multilayer wiring apparatus disclosed in Japanese unexamined patent publication No. 2003-249559, a plurality of wiring layers having a plurality of wirings each arrayed with pitches in an identical direction laminated so that pitch-arraying directions thereof mutually cross are provided, and these wiring layers are connected to each other in a longitudinal direction via a plurality of contact portions. Different first and second potentials are thereby supplied to adjacent wirings, respectively, to form a capacitance element. In addition, by releasing supply of the first and second potentials by eliminating the contact portions, signal lines can be passed in a crossing manner in a capacitance wiring area.
In a semiconductor device disclosed in Japanese unexamined patent publication No. 2004-241762, a plurality of wiring layers laminated to each other are provided, and each wiring layer includes an interlayer insulating film, first and second electrodes buried in this interlayer insulating film and separated from each other, first vias that connect the first electrodes and first electrodes of the wiring layer provided as an upper or lower layer thereof to each other, and second vias that connect the second electrodes and second electrodes of the wiring layer provided as an upper or lower layer thereof to each other, the first electrodes and the first vias are connected to a first terminal, the second electrodes and the second vias are connected to a second terminal, and a capacitor is formed between the first electrodes and the first vias and second electrodes and the second vias.
In addition, Japanese unexamined patent publication No. 2001-177056 can be mentioned as another related art.